Dynamic Flip-Flop with Improved Power

摘要

An improved design of a dynamic Flip-Flop is presented. Proposed design overcomes the problem of the glitch at the output and improves Power-Delay Product for about 10%, while preserving logic embedding property. This is accomplished by equalizing the t_(pLH) and t_(pHL) of the flip-flop and careful design of keeper elements in the circuit. New design introduces insignificant area increase.