Single Event Upset Detection and Correction in Virtex-4 and Virtex-5 FPGAs

摘要

A design for the detection and correction of single event upsets (SEUs) in the configuration memory of field programmable gate arrays (FPGAs) is presented. Larger configuration memories and shrinking design rules have caused concerns to rise about SEUs in high-reliability high-availability systems using FPGAs. We describe the operation and architecture of the proposed design as well as its implementation in Xilinx Virtex-4 and Virtex-5 FPGAs.