Optimal Micro-Threads Scheduling for Multi-Core Processors to Hide Memory Latency

摘要

Multi-core processors are now the standard way to keep Moore's law and manufacture faster and cheaper microprocessors every year. However, current parallelization run-time models, such as PThreads or OpenMP, do not fully utilize multi-core processors' computing power. There is still room to improve multi-core processors' performance through utilizing finer grained threading models. We proposed the micro-threading model as a potential solution to the critical problem of memory latency [1][2]. Such solution dynamically hides at run-time memory latency that would degrade application's performance by large magnitudes. We reached three to five folds performance improvement on different classes of algorithms, such as parallel summation and parallel tree spanning, compared to the current conventional threading models adopting a single thread on each core. In this paper we further build on this model a scheduling algorithm that allows each core reach new performance ceilings given the constraints on utilizing the shared resources on the multi- and many-cores processors. We utilize the Cell Broadband Engine as one of the leading multi-core processors available at the time of this research. We achieved up to 11.6% performance improvement compared to the initial scheduling policy used in our framework.