Dept. of Electrical Engineering Technion - Israel Institute of Technology Haifa 32000, Israel;
Dept. of Electrical Engineering Technion - Israel Institute of Technology Haifa 32000, Israel;
Dept. of Electrical Engineering Technion - Israel Institute of Technology Haifa 32000, Israel;
Dept. of Electrical Engineering Technion - Israel Institute of Technology Haifa 32000, Israel;
clock distribution; non-tree clock networks; clock mesh synthesis; clock skew; process variations; power; VLSI CAD; physical design;
机译:时序驱动的混合网格/树时钟分配网络的变化感知综合
机译:非均匀流量负载下WDM网状环网络的综合和吞吐量行为
机译:MeshWorks:用于优化时钟网格网络综合的综合框架
机译:时序驱动变异感知不均匀时钟网格合成
机译:基于集群的架构,时序驱动打包和FPGA时序驱动布局
机译:使用基于特征的非均匀网格进行3D-2D可变形图像配准
机译:时序驱动变化感知非均匀时钟网格综合