Analytical Modeling of Graded Metal Graded Dielectric Silicon-on-Nothing TFET -A Comparative Study

摘要

In this exertion, the performance of a renovated Tunnel Field Effect Transistor has been examined incorporating the concept of work function engineered gate electrode with binary metal alloy together with linearly graded hetero dielectric pattern (HfO2+SiO2) at front gate and silicon on nothing topology for bottom gate. The model is first simulated using 2-D ATLAS simulator and the simulation results confirmed the effectiveness of the modified TFET structure in terms of improved tunneling efficiency and reduced hot carrier effect. The device also promises to provide required immunity at higher drain bias increasing gate controllability over the channel and offers enhanced ON current to go past the known issue of Low ON current associated with TFET. Now, the complete mathematical model is developed using 2-D Poisson's equation and Kane’s model to derive structural parameters e.g. electrostatic potential, electric field profile and tunneling current of the device. The solution of these potential, field and current expressions were obtained with the help of popular parabolic approximation technique and appropriate initial and boundary conditions. Comparison of these analytical results with simulated data is executed for validation of the reported structure. Thus, the device exhibits higher potential overshoot and greater electric field at source-channel interface and lower field at drain side suppressing various unwanted SCEs, thus can be considered as a suitable alternative for low power VLSI circuits.