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Optimal metastability-containing sorting networks

机译:包含最佳亚稳态的分类网络

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摘要

When setup/hold times of bistable elements are violated, they may become metastable, i.e., enter a transient state that is neither digital 0 nor 1 [1]. In general, metastability cannot be avoided, a problem that manifests whenever taking discrete measurements of analog values. Metastability of the output then reflects uncertainty as to whether a measurement should be rounded up or down to the next possible measurement outcome. Surprisingly, Lenzen & Medina (ASYNC 2016) showed that metastability can be contained, i.e., measurement values can be correctly sorted without resolving metastability first. However, both their work and the state of the art by Bund et al. (DATE 2017) leave open whether such a solution can be as small and fast as standard sorting networks. We show that this is indeed possible, by providing a circuit that sorts Gray code inputs (possibly containing a metastable bit) and has asymptotically optimal depth and size. Concretely, for 10-channel sorting networks and 16-bit wide inputs, we improve by 48.46% in delay and by 71.58% in area over Bund et al. Our simulations indicate that straightforward transistor-level optimization is likely to result in performance on par with standard (non-containing) solutions.
机译:当违反双稳态元件的建立/保持时间时,它们可能变为亚稳态,即进入既不是数字0也不是数字1的瞬态。通常,亚稳是无法避免的,这个问题在每次对模拟值进行离散测量时都会出现。然后,输出的亚稳定性反映了不确定性,该不确定性是应该将测量结果向上舍入还是向下舍入到下一个可能的测量结果。出乎意料的是,Lenzen&Medina(ASYNC 2016)表明可以包含亚稳性,即可以在不首先解决亚稳性的情况下正确分类测量值。但是,无论是他们的工作还是Bund等人的最新技术。 (DATE 2017)此类解决方案是否可以像标准分拣网络一样小和快速地开放。通过提供一个对格雷码输入(可能包含一个亚稳态位)进行排序并具有渐近最佳深度和大小的电路,我们证明了这确实是可能的。具体而言,对于10通道分类网络和16位宽的输入,与Bund等人相比,我们的延迟提高了48.46%,面积提高了71.58%。我们的仿真表明,简单的晶体管级优化可能会导致性能与标准(非包含)解决方案相提并论。

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