Nanoelectronics and VLSI Laboratory, Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Jabalpur, 482005, India;
Nanoelectronics and VLSI Laboratory, Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Jabalpur, 482005, India;
Nanoelectronics and VLSI Laboratory, Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Jabalpur, 482005, India;
Nanoelectronics and VLSI Laboratory, Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Jabalpur, 482005, India;
Nanoelectronics and VLSI Laboratory, Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Jabalpur, 482005, India;
Nanoelectronics and VLSI Laboratory, Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Jabalpur, 482005, India;
Nanoelectronics and VLSI Laboratory, Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Jabalpur, 482005, India;
TFETs; Plasma temperature; Temperature; Silicon; Logic gates; Tunneling; Temperature sensors;
机译:基于三重材料栅极掺杂隧道场效应晶体管的设计与模拟性能分析
机译:Si 0.6 Ge 0.4异质结的少掺杂隧道场效应晶体管,用于改善开关电流比和模拟/ RF性能
机译:较小隧道碳纳米管场效应晶体管的提议
机译:基于温度的掺杂隧道场效应晶体管性能分析
机译:基于石墨烯的隧道场效应晶体管的加速缺陷分析和建模。
机译:用于室温隧穿场效应晶体管的新型柔性通道
机译:掺杂较少的隧道场效应晶体管通过紧凑型Si漏极框架/ Si0.6Ge0.4-Channel / GE源