A novel implementation of mixed ISA on FPGA

摘要

Now a days the requirement of higher performance and more functionality is needed in most of the systems so that the major issue for processor and controller design is power consumption. Normally all the integrated systems are working with batteries, if these systems are consuming more power, maintenance of the battery increases as well as the battery also decreases. So there is need of less power consumed processor or controller for any integrated embedded system. In this paper Novel architecture is proposed and implements a mechanism which combines controller concepts and processor concepts with the help of clock gating technique called Mixed ISA (Mixed Instruction Set Architecture) implemented on FPGA. In this architecture, control unit with dynamic behavior and having a program flow controller, and port controller. The control units power is expected be reduced after applying the clock gating technique. The designed Architecture is implemented on Xilix platform using verilog HDL.