Electronics and Telecommunication Engineering Dept., Indian Institute of Engineering, Science and Technology, Shibpur, Howrah-711103;
Electronics and Telecommunication Engineering Dept., Indian Institute of Engineering, Science and Technology, Shibpur, Howrah-711103;
Electronics and Telecommunication Engineering Dept., Indian Institute of Engineering, Science and Technology, Shibpur, Howrah-711103;
Discrete wavelet transforms; Computer architecture; Hardware; Delays; Adders; Two dimensional displays; Algorithm design and analysis;
机译:使用改进的提升方案的1D和2D DWT架构的FPGA实现
机译:用于实时图像分解的1D / 2D可重新配置的9/7和5/3 DWT过滤器的内存和区域高效分布式算术基于模块化VLSI架构,用于实时图像分解
机译:基于提升的1D / 2D离散小波变换的高效VLSI架构
机译:使用投机加法器的修改提升的乘法器较少的VLSI架构的修改提升1D / 2D DWT
机译:提升方案DWT的VLSI设计优化。
机译:改进的基于2D-DWT的WαSH特征匹配的立体遥感影像
机译:基于提升的1D / 2D / 3D DWT-IDWT体系结构图像压缩的快速实现
机译:使用双重,正常或标准基础的有限域乘法器的VLsI结构的比较