1D-DWT AND 2D-DWT ARCHITECTURE WITH ENHANCED SPEED

摘要

ABSTRACT According to one aspect of the present disclosure, the arithmetic operations of the 1D-DWT architecture may be built by using only adders and shifters instead of multipliers which decreases the hardware complexity. The buffers present in 1D-DWT may allow only positive coefficients to generate low pass and high pass filter outputs. In 2D-DWT architecture, two 1D-DWT blocks may be used. The four subbands LL, LH, HL and HH may be generated due to parallel processing of 2D-DWT thus by increase the speed. According to another aspect of the present disclosure, the row and column signals may read directly hence eliminating the temporary buffer to store the input data. The speed of the architecture may be 260MHz. Thus the architecture may efficient and optimize d in terms of hardware and speed.