A 1.8mW 450-900MHz ±15ps period jitter programmable multi-output clock generator with high supply noise tolerance in 28-nm CMOS process

摘要

Systems-On-Chip (SOC) solutions for flash memory controllers often require multiple clocks with different frequencies for various sub-systems to achieve optimal performance. Traditionally this is achieved by multiple oscillators (RC or LC based) or Phase-Locked-Loops (PLLs) or Multiplying-Delay-Locked-Loops (MDLLs). Another popular approach is a single PLL with multiple open-loop fractional-dividers. In this paper, we propose an area and power efficient scheme to generate multiple clocks at different frequencies using a single PLL loop with multiple Voltage-Controlled-Oscillators (VCOs). The solution also offers higher supply noise immunity. Moreover, control logic is in-built to make multiple frequency outputs programmable to allow SOC performance optimization depending on Process, Voltage and Temperature. The circuit is designed in a standard 28nm CMOS technology and works with 0.9V digital supply.