首页> 外文会议>2017 IEEE 24th International Conference on High Performance Computing >Expander: Lock-Free Cache for a Concurrent Data Structure
【24h】

Expander: Lock-Free Cache for a Concurrent Data Structure

机译:扩展器:并发数据结构的无锁缓存

获取原文
获取原文并翻译 | 示例

摘要

Parallel programming models and paradigms are increasingly becoming more expressive with a steady increase in the number of cores that can be placed on a single chip. Concurrent data structures for shared memory parallel pro- grams are now being used in operating systems, middle-ware, and device drivers. In such a shared memory model, processes communicate and synchronize by applying primitive operations on memory words. To implement concurrent data structures that are linearizable and possibly lock-free or wait-free, it is often necessary to add additional information to memory words in a data structure. This additional information can range from a single bit to multiple bits that typically represent thread ids, request ids, timestamps, and other application dependent fields. Since most processors can perform compare-And-Set (CAS) or load-link/store-conditional (LL/SC) operations on only 64 bits at a time, current approaches either use some bits in a memory word to pack additional information (packing), or use the bits to store a pointer to an object that contains additional information (redirection), and the original data item. The former approach restricts the number of bits for each additional field and this reduces the range of the field, and the latter approach is wasteful in terms of space. We propose a novel and universal method called a memory word expander in this paper. It caches information for a set of memory locations that need to be augmented with additional information. It supports traditional atomic get, set, and CAS operations, and tries to maintain state for a minimum number of entries. We experimentally demonstrate that it is possible to reduce the runtime memory footprint by 20-35% for algorithms that use redirection. For algorithms that use packing, the use of the EXPANDER can make them feasible. The performance overhead is within 2-13% for 32 threads. When we compare the performance of the EXPANDER based non-blocking algorithms with the version that uses locks, we have a performance gain of at least 10-100X.
机译:随着可放置在单个芯片上的内核数量的稳定增长,并行编程模型和范例正变得越来越具有表现力。共享内存并行程序的并发数据结构现在正在操作系统,中间件和设备驱动程序中使用。在这种共享内存模型中,进程通过对内存字应用原始操作来进行通信和同步。为了实现可线性化并可能无锁或无等待的并发数据结构,通常需要向数据结构中的存储字添加其他信息。此附加信息的范围可以从单个位到多个位,通常代表线程ID,请求ID,时间戳和其他与应用程序相关的字段。由于大多数处理器一次只能对64位执行比较设置(CAS)或加载链接/存储条件(LL / SC)操作,因此当前方法要么使用存储字中的某些位来打包其他信息(包装),或使用这些位存储指向包含其他信息(重定向)和原始数据项的对象的指针。前一种方法限制了每个附加字段的位数,这减小了字段的范围,而后一种方法在空间方面是浪费的。在本文中,我们提出了一种新颖的通用方法,称为存储字扩展器。它为需要增加其他信息的一组存储位置缓存信息。它支持传统的原子获取,设置和CAS操作,并尝试为最少数量的条目维护状态。我们通过实验证明,对于使用重定向的算法,可以将运行时内存占用空间减少20-35%。对于使用打包的算法,使用EXPANDER使其可行。 32个线程的性能开销在2-13%之内。当我们将基于EXPANDER的非阻塞算法的性能与使用锁的版本进行比较时,我们可以获得至少10到100倍的性能提升。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号