An industrial design methodology for the synthesis of OCV-aware top-level clock tree

摘要

In modern VLSI Design, on-chip-variation (OCV) has become serious as the feature size continues to shrink. Especially, in the top-level clock tree, OCV-induced clock skew should be properly controlled because of long wires. In this paper, we present a practical industrial design methodology for minimizing the OCV-induced clock skew of top-level clock tree. Our basic idea is to pre-place guide buffers for clock tree synthesis so that wire lengths of non-common paths can be reduced. We develop a novel algorithm to determine the number and the locations of guide buffers. Experiments with an industry chip show that our approach can greatly reduce the percentages of non-common paths (in the overall path) and thus the reduction on OCV-induced clock skew achieves 42.4%.