Electronics and Communication Engineering Department, Motilal Nehru National Institute of Technology Allahabad, Allahabad, India;
Electronics and Communication Engineering Department, Motilal Nehru National Institute of Technology Allahabad, Allahabad, India;
Electronics and Communication Engineering Department, Motilal Nehru National Institute of Technology Allahabad, Allahabad, India;
Electronics and Communication Engineering Department, Motilal Nehru National Institute of Technology Allahabad, Allahabad, India;
Latches; Delays; Transistors; Discharges (electric); CMOS technology; Simulation; Power dissipation;
机译:新型CMOS双尾动态比较器中的偏移和反冲噪声的优化:一种采用批量驱动负载的低功耗,高速设计方法
机译:低功耗高速CMOS双尾动态比较器,使用自偏置放大阶段和新型闩锁阶段
机译:一种新颖的低功耗,低失调和高速CMOS动态锁存比较器
机译:使用小说闩锁结构设计低功耗高速双尾动态CMOS比较器
机译:低功耗高速低偏移完全动态CMOS锁存器
机译:0.18 µm CMOS工艺中的高速,低偏移动态锁存比较器的设计
机译:0.18μmCmOs工艺中高速低偏移动态锁存比较器的设计。