A power-delay efficient carry select adder

摘要

Adders are basic building blocks of any processor or data path application. Adders are not only used for addition, but for many other functions such as subtraction, multiplication and division. For fast arithmetic operations the use of high speed adders is a requirement. Therefore, design of high speed adders with minimum power consumption are essential for the design of high speed arithmetic units. Carry Select Adder (CSA) is one of the fastest adders used in many data processing applications. In this paper we proposes power-delay efficient design of CSA using Manchester carry chain(MCC) in multioutput domino CMOS. This proposed work evaluates the performance of the proposed CSA designs in terms of speed, power consumption, hardware overhead and power delay products in a standard 45nm CMOS technology. The simulation results confirms that the proposed CSA structure has significantly less PDP (Power Delay Product) and hardware overhead than existing standard adder circuits.