Through cavity core device-embedded substrate for ultra-fine-pitch Si bare chips; (Fabrication feasibility and residual stress evaluation)

摘要

We demonstrate the concept and fabrication of through cavity core device-embedded substrate (DES) for fine-pitch Si bare chips with pad pitches up to 60 μm. In order to investigate the fabrication feasibility and process keys, we embedded a Si test element group (TEG) inside a through cavity of 150μm thick core substrate. To adjust the thickness, Si chip was thinned to 120 μm, not including bump height. After placing a chip, the cavity is filled by laminating a two-layer structure ABF (Ajinomoto build-up film) from both sides of the core substrate. Accurate alignment of the chip in the cavity was the most important process parameter to obtain high production yield. The demanded alignment was fulfilled by strictly controlling the lamination conditions and curing temperature of the epoxy resin. Finally, the cavity core type device embedded substrate was compared to the surface mounted type device embedded substrate in regard to the process residual stress using piezo-resistive gauge embedded Si TEG chip.