Emerging Nanoscaled Integrated Circuits Syst. Lab., Bar-Ilan Univ., Ramat Gan, Israel;
CMOS memory circuits; Monte Carlo methods; SRAM chips; data integrity; integrated circuit design; low-power electronics; radiation hardening (electronics); transistors; CMOS process; Monte Carlo simulations; SEU; advanced process technology; continuous transistor; data integrity; integrated circuits; low power SRAM design; memory arrays; memory cell design; memory radiation hardening bitcell solutions; silicon die; single event upset mitigation; size 65 nm; slightly scaled supply voltages; space applications; Logic gat;
机译:由于包含SEL缓解设计的90nm COTS SRAM中的局部闩锁,导致单事件群集多位不安
机译:商业批量65nm CMOS SRAM和触发器中的单事件翻转和多单元翻转建模
机译:CMOS SRAM中单事件闩锁和单事件翻转的微束映射
机译:低功耗SRAM设计的单一事件镦锻缓解
机译:SRAM的体系结构设计,具有片上错误检测和针对单事件翻转的纠正功能。
机译:缓解癫痫神经刺激器的位翻转或单事件不适
机译:使用FLIppER故障注入平台评估基于sRam的FpGa的单事件扰乱缓解方案