High-speed FPGA implementation of an improved LMS algorithm

摘要

The FPGA implementation of a new parallel processing method is studied by introducing the parallel processing method into the delayed least mean square (DLMS) algorithm. The parallel delayed least mean square (PDLMS) algorithm has the faster data throughput and higher convergence rate than the DLMS algorithm. In this paper, the hardware implementation of PDLMS is realized by hardware description language, while the simulation structure is presented. The results show that the PDLMS algorithm has certain superiority according to DLMS.