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CMOS APS with in-pixel discrimination and improved rolling shutter architecture for charged particle tracking

机译:具有像素内识别能力的CMOS APS和改进的卷帘快门架构,用于带电粒子跟踪

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The tradeoff between readout speed, granularity, power consumption, material budget and radiation hardness has balanced in favor of CMOS Active Pixel Sensor (APS) technology for the pixel detector of the incoming ALICE Muon Forward Tracker experiment. In order to avoid pile-up effects in HL-LHC, the classical rolling shutter readout system of CMOS APS, dedicated to charged particle tracking, should be improved to overcome the readout speed limit induced by the row by row signal processing. The proposed solution is based on a novel pixel design including the sensing diode, the analogue signal amplification, a correlated double sampling circuit and an auto-zeroed differential discriminator, all within a 25 µm pitch square pixel. The resulting Rolling Shutter Binary Pixel architecture (RSBPix) allows more than two rows being readout simultaneously. This paper presents a RSBPix prototype designed and fabricated in a 0.18 µm CMOS Image Sensor process. A description of the ASIC architecture is provided, followed by the detailed test results from laboratory measurements. First achievements of a low temporal and fixed pattern noise, fast readout speed (160 ns per row) digital pixel are shown.
机译:读出速度,粒度,功耗,材料预算和辐射硬度之间的权衡已得到平衡,有利于CMOS有源像素传感器(APS)技术用于即将来临的ALICE Muon前向跟踪器实验的像素检测器。为了避免HL-LHC中的堆积效应,应改进专用于带电粒子跟踪的CMOS APS经典卷帘读出系统,以克服逐行信号处理引起的读出速度限制。提出的解决方案基于一种新颖的像素设计,包括感测二极管,模拟信号放大,相关的双采样电路和自动归零的差分鉴别器,所有这些都在25 µm间距的正方形像素内。由此产生的滚动快门二进制像素架构(RSBPix)允许同时读取多于两行。本文介绍了采用0.18 µm CMOS图像传感器工艺设计和制造的RSBPix原型。提供ASIC架构的描述,然后是实验室测量的详细测试结果。显示了低时间和固定模式噪声,快速读出速度(每行160 ns)数字像素的初步成就。

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