A Region-Based Framework for Design Feature Identification of Systematic Process Variations

摘要

Process monitoring circuitry such as ring oscillators or delay-test-based diagnosis method has been applied to characterize process variations of a chip. For a design process, it is also desirable to consider circuit features that might cause such a systematic process variation. In this paper, we use the variation map built from measured excessive delays to analyze the correlation between circuits and systematic variations. With support vector regression, a physical map of a circuit is partitioned into different regions that are inherently affected by similar causes. And then possible features (e.g., cell types, layout characteristics, etc.) that influences these regions are ranked. Experimental results show that the proposed method can effectively identify process regions and rank major features at top orders with injected variations.