2.5D integration is emerging as a precursor to stacked 3D ICs. Since the silicon interposer and micro-bumps in 2.5D integration can suffer from fabrication and assembly defects, post-bond testing is necessary for product qualification. This paper proposes and evaluates an interposer test architecture based on extensions to the IEEE 1149.1 Std. The proposed method enables access to interconnects inside the interposer by probing on the C4 bumps. It provides an effective test method for opens, shorts, and interconnect delay fault in the interposer. Moreover, micro-bumps can be tested through test paths that include dies on the interposer. HSPICE simulation results show that a large range of defects can be detected, diagnosed, and characterized using the proposed approach.
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