A 28nm 6T SRAM memory compiler with a variation tolerant replica circuit

摘要

We propose an SRAM replica tracking circuit that reduces divergence of the replica path relative to normal read path (6–16% less Sense differential Requirement), thus improving the access time by 5–8%. The approach is compatible to power managed SRAMs having Retain till Access feature and also for non power managed SRAMs with no sense differential impact. Using This Replica tracing circuit Sense differential has been well tracked across all array and periphery voltages combinations which further improve the access time by 4–6%. Instances with this method 0.5–256Kb have been tested on a 28nm CMOS LP process.