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Open loop approach to design low voltage, 400 mV, 1.3 mW, 10 GHz CMOS class-B VCO

机译:开环设计低电压,400 mV,1.3 mW,10 GHz CMOS B类VCO

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摘要

The paper presents a method for design of LC cross-coupled oscillators based on an open loop technique and its practical application leading to a high frequency CMOS oscillator prototype. Thanks to the proposed approach, the main circuit parameters such as loaded quality factor (responsible for phase noise performance of LC oscillator) and steady-state oscillation amplitude, can be extracted without the necessity of time consuming transient simulations. The presented method is not technology specific and allows fast calculations under changing bias conditions. The proposed 130 nm CMOS prototype operates at 10 GHz from a 400m V power supply achieving an average SSB phase noise of −110 dBc/Hz at 1 MHz offset from the carrier and a fractional bandwidth of more than 7.5%. Low average power consumption of 1.3 mW RMS, has been obtained by biasing the oscillator devices to operate in class-B i.e. VGS = VDD = Vth.
机译:本文提出了一种基于开环技术的LC交叉耦合振荡器的设计方法及其在高频CMOS振荡器原型中的实际应用。由于采用了所提出的方法,因此可以提取主电路参数,例如负载质量因数(负责LC振荡器的相位噪声性能)和稳态振荡幅度,而无需进行耗时的瞬态仿真。提出的方法不是特定于技术的,并且允许在变化的偏置条件下进行快速计算。拟议的130 nm CMOS原型采用400m V电源在10 GHz频率下工作,在距载波1 MHz处偏移时,平均SSB相位噪声为-110 dBc / Hz,分数带宽超过7.5%。通过使振荡器器件偏置以在B类下工作,即VGS = VDD = Vth,已获得1.3 mW RMS的低平均功耗。

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