Reduced Complexity On-chip IQ-Imbalance Self-Calibration

摘要

The architectural simplicity of the direct-conversion scheme makes it an appealing architecture for low cost and low power transceivers. This architecture however demonstrates increased sensitivity to analog front-end impairments, such as gain and phase imbalance in the transceiver's in-phase and quadrature (IQ) paths. Especially when used in flexible software-defined radios, very fast, but low cost IQ-imbalance estimation and correction methods are required, to cope with the dynamically varying IQ imbalance due to environmental effect and frequency shifts. The main goal of this paper is to present an on-chip, off-line, extremely fast and low complexity self-calibration of IQ imbalance and carrier feed through for both the transmitter and receiver. Custom-designed training symbols allow to reduce the computational complexity, such that the calibration method can be performed at any user defined instance in negligible time. The reported complexity analysis shows that the whole calibration process takes up less than 4000 processor cycles, or 16us, when running on an OPENRISC 1200 core.