This paper proposes IR-drop reduction of sub-VT circuits by de-synchronization. The de-synchronization concept is briefly demonstrated and analyzed by a case study. Extensive IR-drop analysis' of various technology options of a 65nm CMOS family demonstrate how the noise margins are reduced due to switching noise on the supply rails. It is shown that a de-synchronized implementation reduces severe voltage drops on the supply rails by approximately 50 %, compared to a clocked design.
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机译：本文提出了通过去同步来降低sub-V T 电路的IR压降的方法。通过案例研究简要演示和分析了非同步概念。对65nm CMOS系列的各种技术选择进行的广泛的IR压降分析表明，由于电源轨上的开关噪声，如何降低噪声容限。结果表明，与时钟设计相比，去同步的实现方式可将电源轨上的严重电压降降低约50％。
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