A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2

摘要

In this paper, a clock and data recovery (CDR) circuit that supports triple data rates of 1.62, 2.7 and 5.4Gbps for DisplayPort 1.2 standard is described. The proposed CDR circuit employs a dual-loop architecture that includes a phase-locked loop and a frequency-locked loop. The circuit with a half-rate phase detector has a triple-mode voltage-controlled oscillator (VCO) which changes the operating frequency by 3bit code. The prototype chip is designed and verified using a 65nm CMOS technology. The recovered-clock jitter with the data rates of 1.62/2.7/5.4Gbps at 2³¹-1 PRBS is measured to 7/5.6/4.7psrms, respectively, while consuming 11mW with a 1.2V supply.