High-speed clock and data recovery circuits for random non-return-to-zero data.

摘要

The rapid increase of real-time audio and video transport over the internet has led to a global demand for high-speed serial-data communication networks. To accommodate the required bandwidth, an increasing number of wide area networks (WANs) and local area networks (LANs) are converting the transmission medium from a copper wire to fiber. This trend motivates research on low-cost, low-power integrated fiber-optic receivers. A critical task in such receivers is the recovery of the clock embedded in the non-return-to-zero (NRZ) serial-data stream. The recovered clock both removes the jitter and distortion in the data and retimes it for further processing.; The research objective of this thesis is to analyze, design, and implement highspeed clock and data recovery circuits for 2.5-Gb/s optical fiber receivers that can be readily implemented in an integrated, low-cost, low-power CMOS technology. Our primary contributions to this research include the design methodology and implementation of two clock recovery circuits fabricated in both 0.4-μm and 0.25-μm digital CMOS technologies without the aide of external references. The circuit designed in the 0.4-μm CMOS is limited by the achievable technology bandwidth. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide tuning range. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS of length 27 − 1. The core circuit dissipates a total power of 33.5 mW from 3.3-V supply and occupies an area of 0.8 × 0.4 mm2. The system design in the 0.25-μm CMOS includes both a frequency-locked loop (FLL) loop as well as a phase-locked loop (PLL) to increase the frequency acquisition range of the circuit with no external reference. To achieve a wide tuning range with low phase noise, an LC-oscillator is employed with a digital capacitor array. The recovered clock exhibits an rms jitter of 5.1 ps for a PRBS of length 223 − 1. This circuit core dissipates 55 mW of power from a 2.5 V supply and occupies a core area of 0.9 × 0.6 mm 2.