High power, high efficiency stacked mmWave Class-E-like power amplifiers in 45nm SOI CMOS

摘要

Stacking devices in CMOS power amplifiers (PAs) increases the achievable output voltage swing, thereby increasing the output power and efficiency, particularly at millimeter-wave frequencies. This work presents stacked CMOS PAs based on an improved Class-E design methodology, where device loss is explicitly accounted for in the analysis and design procedure. Design guidelines and fundamental limits on achievable performance are presented. Two fully-integrated 45GHz prototypes with 2 and 4 stacked devices have been fabricated in IBM's 45nm SOI CMOS technology. Measurement results yield a peak PAE of 34.6% for the 2-stacked PA with a saturated output power of 17.6 dBm, and a peak PAE of 19.4% for the 4-stacked PA with a saturated output power of 20.3 dBm. The former represents the highest PAE reported for CMOS mmWave PAs, and the latter represents the highest output power achieved from a CMOS mmWave PA. The paper also describes the modeling of active and passive devices for mmWave CMOS PAs for good model-hardware correlation.