Packet classification is a fundamental enabling function for various applications in switches, routers and firewalls. Due to their performance and scalability limitations, current packet classification solutions are insufficient in ad-dressing the challenges from the growing network bandwidth and the increasing number of new applications. This paper presents a scalable parallel architecture, named Para Split, for high-performance packet classification. We propose a rule set partitioning algorithm based on range-point conversion to reduce the overall memory requirement. We further optimize the partitioning by applying the Simulated Annealing technique. We implement the architecture on a Field Programmable Gate Array (FPGA) to achieve high throughput by exploiting the abundant parallelism in the hardware. Evaluation using real-life data sets including Open Flow-like 11-tuple rules shows that Para Split achieves significant reduction in memory requirement, compared with the-state-of-the-art algorithms such as Hyper Split [6] and EffiCuts [8]. Because of the memory efficiency of Para Split, our FPGA design can support in the on-chip memory multiple engines, each of which contains up to 10K complex rules. As a result, the architecture with multiple Para Split engines in parallel can achieve up to Terabit per second throughput for large and complex rule sets on a single FPGA device.
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