Partitioning and context switching for a reconfigurable FPGA-based DAB receiver

摘要

The sequential execution of processing elements by time-multiplexing FPGA resources using single-island partial reconfiguration allows for resource-efficient designs in comparison to static FPGA implementations. Designing a processing chain for such a system requires the chain to be partitioned into reconfigurable modules, which can be sequentially executed. For this task, we will present an approach to partition an existing digital signal processing chain into separate modules with the goal to obtain a balanced logic occupation. Furthermore, we will show how the overhead of context switching can be reduced by frame-aware data processing and we will introduce a context-annotation scheme for synchronous data flow graphs. After applying our findings to a reconfigurable digital audio broadcasting receiver and quantifying the benefits and drawbacks of time-multiplexed execution, we will finally show that the time-multiplexed execution of receiver components decreases the resource consumption as compared to the static design.