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A high CMRR analog front-end IC for wearable physiological monitoring

机译:用于穿戴式生理监测的高CMRR模拟前端IC

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This paper presents a High Common Mode Rejection Ratio(CMRR) Instrumentation Amplifier(IA) with Driven Right Leg(DRL) circuitry for Electrocardiogram(ECG) signal acquisition. The circuit is based on the current feedback topology. The high pass and lowpass filters are integrated into the IA. DRL is implemented to minimise the common mode noise. The present design is fabricated at UMC on 0.18µm CMOS process technology. The measured CMRR of the circuit is 122dB. The bandwidth of the amplifier is 0.05–125Hz. The integrated input referred noise is 2.3µV. the ICMR is 0–1.65V and the dynamic range is +4.5mV. The power of the total circuit(IA+DRL) is 132µW with a 3.3V supply. The instrumentation amplifier is tested with simulators and patients also.
机译:本文提出了一种带有驱动右腿(DRL)电路的高共模抑制比(CMRR)仪表放大器(IA),用于心电图(ECG)信号采集。该电路基于电流反馈拓扑。高通和低通滤波器已集成到IA中。实施DRL是为了使共模噪声最小。本设计是在联电采用0.18µm CMOS工艺技术制造的。测得的电路CMRR为122dB。放大器的带宽为0.05–125Hz。集成输入参考噪声为2.3µV。 ICMR为0-1.65V,动态范围为+ 4.5mV。采用3.3V电源时,整个电路的功率(IA + DRL)为132µW。仪表放大器也经过模拟器和患者的测试。

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