Design-friendly scalability of cost-effective 28LP technology platform featuring 2^nd generation gate-first HK/MG transistors without eSiGe

摘要

Scalability of the 28nm gate-first high-k/metal gate (HK/MG) LP devices with maintaining the performance and layout flexibility was comprehensively studied for the first time. We demonstrated the N-/PFET drive current (Idsat) of 0.86/0.46 mA/µm with the off-leakage current (Ioff) of 1 nA/µm for the supply voltage (Vdd) of 1V by the simple method suitable for scaling the circuit area whereas the local fluctuation in threshold voltage (Vt) was reduced (Avt(N/P)=1.45/1.55, which could make the SRAM cell size scaled down by 6%). We investigated the dependence of the electrical characteristics of such gate-first HK/MG devices on both the gate width (Wg) and gate pitch (Pgg) to show the geometric scalability of the gate electrode. We also evaluated the dependence of them on both the length of active region (LOD) and distance between two active regions to show the scalability of the active region for increasing the transistor density. Finally, we found that the systematic variation related with the flexible gate layout could be suppressed.