Miniaturization of Printed Wiring Board Assemblies into System in a Package(SiP)

摘要

The demand for system miniaturization in many applications has lead to efforts to put all or most of the functions on a single chip. However, there are many situations where this is not possible or cost prohibitive. Memory uses large amounts of chip area and several different memory types may be needed to fulfill the functional requirements. In many cases, the need for analog and digital functions may make consolidation on a single chip impossible. An alternate approach is to preserve the proven functional design and miniaturize at the package level to achieve the desired space savings. The approaches explored in this publication include eliminating active chip packages by directly attaching the chip to the SiP with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. A further benefit of the SiP is a major reduction in total height. Two specific cases will be detailed and the size reductions shown. The concept of a SiP index will be introduced to show how the SiP area compares to active die area. The miniaturized SiP with its reduced package size and demand for passives requires a high wireability package with embedded passives and excellent communication from top to bottom. Endicott Interconnect Technologies has a Core EZ? package [1] that meets these requirements. The details of the package design parameters and package electrical performance are demonstrated.