3D Thermal Stress Models for Single Chip SiC Power Sub-Modules

摘要

Three dimensional models of single chip SiC power sub-modules were generated using ANSYS in order to simulate the effects of various substrate materials, heat fluxes, and heat transfer coefficients on temperature and thermal stress contours. Silicon nitride, aluminum-nitride, alumina were compared as substrates with or without an additional layer of CVD diamond on either top or bottom of the surfaces. Simulated heat fluxes of 100 to 300 watts/cm2 resulted in device junction temperatures in the range of 359 to 7289 K. With modest cooling, represented by a heat transfer coefficient (hconv) of 3350 watts/m~2-K, SiC chips operated at 300 watts/cm~2 power density maintained junction temperatures T_j < 688 K. In the applied heat flux range, the maximum Von Mises stress of a simulated single SiC device sub-module was between 767 MPa to 54.9 GPa. Whereas, the maximum shear stress was between 153 MPa and 8.1 GPa. Regardless of stacking configuration, the maximum chip temperature, Von Mises stress, and shear stress decreased with increasing heat transfer coefficient from 50 to 5000 watts/m~2-K. If consistent with simulation results, CVD diamond integrated substrates should be superior in most cases to those comprised of only AlN, Al_2O_3, and Si_3N_4. Experimental validation of ANSYS results and more extensive multiple-chip power module simulations will be explored.