Fault Tolerant Clockless Wave Pipeline Design

摘要

This paper presents a fault tolerant design technique for clockless wave pipeline.The specific architectural model investigated in this paper is the two-phase clockless wave pipeline[12]which is ideally supposed to yield the theoretical maximum performance.Request signal is the most critical component for the clockless control of the wave pipelined processing of data.In practice,the request signal is very sensitive and vulnerable to electronic crosstalk noise,referred to as glitch,and this problem has become extremely stringent in the ultra-high density integrated circuits today.Electronic crosstalk noise may devastate the operational confidence level of the clock- less wave pipeline.In this context,this paper characterizes the yield and reliability properties of the two-phase clockless asynchronous pipeline with respect to glitch.Based on the yield and reliability characterization,a simple yet effective fault tolerant architecture by using redundant request signals is proposed.The reliability model evaluates the impact of the request signal glitch on the overall reliability,and can be used to maneuver the proposed fault tolerant architecture.An experimental simulation is conducted to demon-strate the efficiency and effectiveness of the proposed fault tolerant technique.