Summary form only given. The major problem regarding hardwareimplementation of neural networks is due to the fact that the number ofinterconnections grow quadratically with the number of pressing elementsin each layer. The hard-limiting neuron model, well suited for digitaltechnology, provides a base for implementing neural networks in hardwaredesigns. A neural-processing chip is developed using this concept. Itlinks neurons along a serial shift register, eliminating the need for anenormous array of interconnecting wires. The neurons process informationin parallel while communicating data serially. Connection weights arestored locally with each neuron, relieving the burden on the networkstructure to maintain weighted connections. Each chip has 16 neurons anda memory holding a 16×128 array for weight. Up to 8 chips can beconnected in tandem, increasing the size of the system to a maximum of128 neurons. Due to the versatile design of the neural-processing chip,it provides a vehicle for researchers to emulate or implement variousneural network architectures
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