Modeling of Self- Mutual-Inductance For Traces Partially Influenced by the Conductive Die Attach in Chip Scale BGA

摘要

The effect of parasitic inductance in the Chip Scale Ball Grid Array, CSBGA, is significant at frequencies of one gigohertz and higher. Modeling of its effect is necessary to optimize its design and simulate the package circuit performance. In this paper, a computer model of the parasitic inductance for the CSBGA is demonstrated. The model considers the significant contributions of the partial ground effect generated by the conductive die attach material on both the self and the mutual inductance. It simplifies the 3D problem into a 2D one rather than using the commonly employed boundary element method, finite difference method, or finite element method. These other methods are usually complicated and require longer run times. This is accomplished by making a smart projection of the trace in three-dimensional space onto a plane. Based on available formulas in the previous references, the self- and mutual-inductance for traces on different layers and with a ground plane formed by the conductive die attach material can be quickly extracted. Finally, these routines are simulated with a commercially available 3D solver program which employs a fast multipole method. The simulation results show that our model is accurate with relative error of less than 10%.