METHOD OF REDUCING THE PATTERN EFFECTS ON B PENETRATION AND TED EFFECT BY IN-SITU POLY DEPOSITION AT WAFER BACKSIDE BEFORE RAPID THERMAL PROCESSING

摘要

In this paper, the pattern effects during rapid thermal processing on boron penetration, oxide integrity and short channel effect are explored. It is observed that the pattern effect will enhance boron penetration around the wafer edge for PMOS transistors. In addition, it is found that the pattern effect will enhance the transient enhanced diffusion (TED) effect for short channel NMOS transistors, and then leads to more V_T roll-off and reduces the device margin. To relieve the pattern effects at the wafer edge, a modified process by in-situ polysilicon deposition at the wafer backside before the spacer etching is proposed and verified by V_T mapping. The improvements of electrical uniformity is attributed to that polysilicon has more uniform emissivity across the wafer backside and the dopant P_(31) in polysilicon can increase the speed of the absorption of radiated photon energy and the conversion to lattice heat across the whole wafer.