Generating PBR Sequences for System Testing at 500megabits/Sec. and Higher Using IC Flip-Flops

摘要

Generating pseudo-random bit sequences at very high bit-rates is limited by the maximum switching speed of shift registers and modulo-2 adders. A system is proposed in which registers composed of integrated circuits, operating near their maximum bit-rate may be combined in parallel to produce sequences at much higher rates.