SOT-MRAM AREA-OPTIMIZED DESIGN OF SOT-MRAM

摘要

A SOT-MRAM area optimization technique is disclosed. A memory device according to an embodiment may include a free layer, a pinned layer, and a magnetic tunnel junction between the free layer and the pinned layer; a metal layer in contact with one side of the free layer of the magnetic tunnel junction; and a spin sink layer (SSL) formed under the metal layer, wherein a low area can be achieved by arranging a source line perpendicular to a bit line in the memory device, and the memory device for a read operation or a write operation in the device The source line configured on the device can be set to ground.