TRIPLE MODULAR REDUNDANCY FOR FAULT-TOLERANT IN-MEMORY COMPUTING

摘要

Methods, systems, and devices related to 3D self- selecting-memory array of memory cells are described. The method relates to a solution for improving the fault-tolerant capability of memory devices, comprising: applying a triple-modular-redundancy calculation in a programming phase of the memory-cells of a memory array; adopting a sequence of two opposite dual polarity algorithms applied along a selected Bit Line and in parallel on the at least three selected Word Lines of the memory array.