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COMPUTE-IN-MEMORY (CIM) CELL CIRCUITS EMPLOYING CAPACITIVE STORAGE CIRCUITS FOR REDUCED AREA AND CIM BIT CELL ARRAY CIRCUITS
COMPUTE-IN-MEMORY (CIM) CELL CIRCUITS EMPLOYING CAPACITIVE STORAGE CIRCUITS FOR REDUCED AREA AND CIM BIT CELL ARRAY CIRCUITS
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机译:计算内存(CIM)单元电路采用电容存储电路,用于缩小面积和CIM位单元阵列电路
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摘要
A CIM bit cell circuit employing a capacitive storage circuit to store a binary weight data as a voltage occupies half or less of the area of a 6T SRAM CIM bit cell circuit, reducing the increase in area incurred in the addition of a CIM bit cell array circuit to an IC. The CIM bit cell circuit includes a capacitive storage circuit that stores binary weight data in a capacitor and generates a product voltage indicating a binary product resulting from a logical AND-based operation of the stored binary weight data and an activation signal. The capacitive storage circuit may include a capacitor and a read access switch or a transistor. The CIM bit cell circuit includes a write access switch to couple a write bit voltage to the capacitive storage circuit. In a CIM bit cell array circuit, the product voltages are summed in a MAC operation.
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