Inductive and capacitive aware methodologies for physical and circuit synthesis of high-speed digital and RF circuits.

摘要

Computer-aided design in VLSI is a continuously evolving subject, with new algorithms and solutions constantly modifying the established norms in order to accommodate efficient strategies to make CAD principles strong at an early phase of design abstraction. The same principle also applies to the routing phase in the physical design of VLSI circuits. There have been several attempts to innovate novel routing methodologies and make it parasitic aware. This awareness in the routing paradigm is important in high-frequency designs, since inductive and capacitive crosstalk that often proved to be crucial in the performance of digital and analog circuits were ignored in previous design attempts.; We added an important flavor to make the interconnect-centric routing more meaningful. Realizing the importance of self and mutual inductance and coupling capacitance between neighboring wires, we introduced a routing approach based on higher order moment metrics, which captures the inductive and capacitive parasitics to form a cost function comprising of a mathematical expression. Minimizing the cost allowed us not only to obtain routes that are inductive and capacitive aware but also that produced the least ringing and delay during signal propagation. To make the route cost function even more robust and efficient, we introduced a concept of parasitic transformation on the universal RLC template required by the moment-driven cost function.; Besides making the routing technique parasitic-aware, we also made the routing methodology suited towards faster convergence, in line with the requirement of an efficient CAD tool. A constraint-driven non-linear algorithm that satisfies the design rule requirements in addition to minimizing the moment-driven cost function using non-linear algorithm, has been developed to serve this purpose.; Layout inclusive synthesis strategies have been present in the domain of Analog and RF synthesis for quite some time. Introducing capacitive and on-chip inductor parasitics helped to bring the parasitic awareness during synthesis and prevented the expensive re-design loop between fabrication and design specification from happening. In order to give the synthesis technique a new dimension and a more refined approach, we implemented a quasi-static extraction strategy in order to extract the resistive, self and mutual inductive parasitics of on-chip inductors and interconnects, within the synthesis flow. (Abstract shortened by UMI.)