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EFFICIENT HARDWARE ACCELERATOR ARCHITECTURE EXPLORATION

机译:高效硬件加速器体系结构探索

摘要

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for determining architectures of hardware accelerators. In one aspect, a method includes receiving data specifying a plurality of hardware parameters; receiving data specifying one or more predetermined values for each of one or more of the plurality of hardware parameters; generating a plurality of candidate hardware architectures that are specific to a particular machine learning task by repeatedly performing the following operations: selecting a respective value for each of the plurality of hardware parameters; determining a candidate hardware architecture; determining whether the candidate hardware architecture satisfies pre-evaluation criteria; and in response to a positive determination, evaluating a performance measure of the candidate hardware architecture on the particular machine learning task; and generating a final hardware architecture based on the plurality of candidate hardware architectures and on the performance measures.
机译:用于确定硬件加速器架构的方法、系统和装置,包括编码在计算机存储介质上的计算机程序。在一个方面,一种方法包括接收指定多个硬件参数的数据;接收为所述多个硬件参数中的一个或多个中的每一个指定一个或多个预定值的数据;通过重复执行以下操作来生成特定于特定机器学习任务的多个候选硬件架构:为多个硬件参数中的每一个选择相应的值;确定候选硬件架构;确定候选硬件架构是否满足预评估标准;以及响应于肯定的确定,评估关于特定机器学习任务的候选硬件架构的性能度量;以及基于所述多个候选硬件架构和所述性能度量生成最终硬件架构。

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