An Ultra-low-power Data Buffer Design for future High-performance DDR6/7 LR-DIMM applications

摘要

An ultra-low-power data buffer for next-generation high-performance DDR6/7 LR-DIMM applications is presented. The ultra-low-power data buffer system for the next-generation high-performance DDR6/7 LR-DIMM application proposed by the present invention receives a low-speed clock input from the CPU and receives the clock from the low-power clocking interface and low-power clocking interface including an additional clock buffer for the high-speed clock. A plurality of DRAMs that receive input and convert to a high-speed clock through ILFM, and a plurality of data buffers that receive clocks from each DRAM and include a transmitter and a receiver, each of the plurality of data buffers includes three inverters and two It includes a transmitter including two resistors, three inverters and two resistors, and a receiver in which the size of the three inverters increases sequentially, and a resistive feedback output driver is used to increase the data rate.