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Apparatuses and methods for providing internal double data rate operation from external single data rate signals
Apparatuses and methods for providing internal double data rate operation from external single data rate signals
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机译:用于从外部单数据速率信号提供内部双数据速率操作的装置和方法
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摘要
In some examples, a memory device may include an internal synchronization circuit that provides for double data rate operation of the memory device when external single data rate signals are provided to the memory device. The external signals may be command and/or address signals provided by an external testing circuits in some examples. The internal synchronization circuit may latch and/or delay at least some of the external signals such that different external commands are provided at the rising and falling edges of the clock signal of the memory device. The memory device may latch the external signals at both the rising and falling edges of the clock signal for double data rate operation of the memory device.
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