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Handling Multiple Graphs, Contexts and Programs in a Coarse-Grain Reconfigurable Array Processor
Handling Multiple Graphs, Contexts and Programs in a Coarse-Grain Reconfigurable Array Processor
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机译:处理粗粒型可重新配置阵列处理器中的多个图形,上下文和程序
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摘要
A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to receive a software program represented as a set of interconnected Data-Flow Graphs (DFGs), each DFG specifying code instructions that perform a respective portion of the software program, to schedule execution of the DFGs in time alternation, and, for each DFG being scheduled, to configure at least some of the compute nodes and interconnects in the compute fabric to execute the code instructions specified in the DFG, and send to the compute fabric multiple threads that each executes the code instructions specified in the DFG.
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