JTAG BASED ARCHITECTURE ALLOWING MULTI-CORE OPERATION

摘要

The present disclosure relates to an apparatus comprising a memory component having an independent structure and including at least an array of memory cells with associated decoding and sensing circuitry, a host device coupled to the memory component through at least a communication channel, a control and JTAG interface in said at least an array of memory cells, and at least an additional register in said control and JTAG interface for handing data, addresses and control signals provided by the host device. The additional register is configured to store at least a page address associated with the array of memory cells, the memory component is configured to load said page address at the power-on of the apparatus, and the host device is configured to perform a read sequence at said page address. A corresponding non-volatile memory device and method are disclosed.