INVERTING WPL GATES WITH EDGE-TRIGGERED READOUT

摘要

A reciprocal quantum logic (RQL) wave-pipeline logic (WPL) inverting gate includes a Josephson junction-based comparator that corrects a design weakness present in other RQL WPL inverting gates that can lead to the propagation of glitches under certain timing conditions. With selective placement of pulse generators at the inputs, the RQL WPL inverting gate can be used to construct A AND (B XOR C) gates, XOR gates, NOT gates, and A-AND-NOT-B gates.