A chip (100) is provided, and includes a first die (110) and a second die (130). The second die (130) is disposed on the first die (110). A filling dielectric layer (140) is further disposed in the chip (100). A through dielectric via (Through Dielectric Via) (150) and an interconnection metal (160) are disposed in the filling dielectric layer (140), and the first die (110) is coupled to the second die (130) through the through dielectric via (150) and the interconnection metal (160). According to the chip (100), a plane area of the chip (100) can be reduced, and manufacturing costs are relatively low.
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